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Compliance analysis performed after or alongside electrical (analog) analysis and consists of: logic (command transfer) verification and timing margin analysis to JEDEC timing specifications. This ensures your target is compliant with JEDEC specification timing requirements and must be done in real time or violations can be missed. Knowing that a violation occurred is a start but the ability to capture bus cycles leading up to the violation and following the violation provides powerful insight into the cause and result of the violation. A memory analyzer is used for compliance analysis. It not only addresses the needs described above but also provides insight into the analog characteristics of all bus signals.